There are various parameters, such as operating frequencies, duty cycle, or potential drop measurements at different nodes inside an integrated circuit, which needs to be analyzed. These parameters are required to understand special characteristics of the Integrated Circuits (ICs). A specific value of an operating frequency and a duty cycle of an on chip clock or signal often become significant in very large scale integration (VLSI), like DRAM circuits and analog to digital conveter (ADC) circuits, which are sensitive to the operating frequency or duty cycle or where operations are synchronized with both transitions of the clock.
There exist many applications where the speed of the I/O structures becomes a limiting factor inside a chip. In such cases identifying the true limits of the operating frequency of the I/O structures with respect to a specified duty cycle and an upper and a lower voltage threshold limit can help the core designer, as he/she exactly knows the limiting frequency of I/Os for applying critical signals like clock and observing the output values. Identifying the true operating frequency in a computer system may prevent inconsistencies between the processor, software running on it, and the generation of operation-code exceptions.
The clock signal is a heart beat for all synchronous digital computing and communication circuits, some of which are sensitive to both edges of the clock. Dynamic and domino logic circuits require one phase of the clock cycle for pre-charge and the other to evaluate, thus imposing a tight constraint on the operating frequency and the duty cycle of the clock to operate at maximum possible speed. In data communication circuits and systems the importance of clock-to-data correlation is magnified, and large variations in these parameters (operating frequency and duty cycle) of the clock cannot be tolerated. Similarly, in serializer/deserializer (SERDES) technology when both edges of the serialization signal are used to serialize the data, a balanced duty cycle becomes very important to provide equal transmission time for each symbol.
In advanced deep submicron VLSI technologies, the clock is distributed to individual components through a large clock distribution tree made up of clock buffers and interconnects of appropriate sizes to minimize skew and end-to-end delay. A noticeable degradation in duty cycle can be observed at the terminal ends of the signal distribution network, even for signals generated with a perfectly stable and accurate signal source. This is due to a slight mismatch in the drive strengths of pull-up and pull-down networks of the CMOS gates/buffers and non-uniformity in the distribution of wiring capacitance. A local duty cycle correction circuit is usually required to fix this problem.
At the tester level, operating frequency measurement can be done only for output I/Os, not for input I/Os. Hence an on chip system is required which would internally measure the operating frequency of an input I/O and generate the result in a digital format.
There exists various conventional techniques for frequency measurement inside a chip, but none of the techniques provide measurement of the true operating frequency, which satisfies a plurality of conditions, such as duty cycle values, upper voltage threshold and lower voltage threshold.
Therefore, there arises a need for a testing methodology for measuring maximum operating frequency and corresponding duty cycle for an input, and output I/O cell. Moreover, the proposed methodology provides an on chip testing flexibility.